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1. Fast Ethernet (10/100) PHY

  • SMIC 0.18um process
  • Support 10/100Mbps TX.
  • Support 802.3 Full-duplex and half-duplex mode.
  • Support auto MDI/MDIX (auto-crossover) function with IEEE 802.3.
  • Fully compliant with IEEE 802.3/802.3u.
  • Support IEEE 802.3u auto-negotiation in TX mode.
  • Support MII / RMII interface.
  • Support automatic receiving/transmitting power saving function.
  • Support 25MHz/50MHz OSC/XTAL input PLL.
  • 100M timing recovery and performance exceeds 110 meters for UTP 5.
  • 10M timing recovery and performance exceeds 140 meters for UTP 5.
  • Support 10M RX/TX jabber monitor functions.
  • Support 10M auto polarity detection function.
  • Support Interrupt function.
  • Support repeater mode.
  • Support Parallel/Serial LED display
  • Single 3.3V power supply with built-in 1.8V regulator.
  • DSP-based PHY Transceiver technology
  • Support flow control to communicate with other MAC through MDC and MDIO

We can provide (1) RTL code; (2) Simulation environment; (3) Synthesize constraint file; (4) Timing analysis constraint file; (5) Netlist file; (6) Netlist simulation environment; (7) GDS hard macro file

2. 8B/10B converter for Giga Fiber

  • Support Gigabit Ethernet Fiber mode 8B/10B converter
  • Support Gigabit Ethernet Fiber mode Auto-negotiation function and negotiation three types medium (FX/CX/LX).
  • Support Gigabit Ethernet Fiber mode synchronization & alignment function.

We can provide (1) RTL code; (2) Simulation environment; (3) FPGA down load file; (4) Synthesize constraint file; (5) Timing analysis constraint file; (6) Netlist file; (7) Netlist simulation environment

3. 10/100/Giga MAC controller

  • Support 10/100 Medium Access Control full/half duplex function.
  • Support 1000 Medium Access Control full duplex function.
  • Support flow control function in all speed full duplex mode.
  • Support back pressure function in 10/100 half duplex mode.
  • Support VLAN tag/un-tag function.
  • Support VLAN port function.
  • Support MII / RMII / SNI / SMII interface.
  • Support VLAN QoS priority function.
  • Support RX/TX pause function in full duplex mode..
  • Support optional CRC check function.
  • Support IPG selection function (88-bit time/96-bit time).
  • Support optional drop/un-drop function after 16 times collision in 10/100 half duplex mode.
  • Support optional CRC generation function.
  • Support MDC/MDIO function to detect the negotiation results.

We can provide (1) RTL code; (2) Simulation environment; (3) FPGA down load file; (4) Synthesize constraint file; (5) Timing analysis constraint file; (6) Netlist file; (7) Netlist simulation environment

4. DP80390 MCU (8051 compatible)

  • Fully software compatible with industry 8051 standard.
  • Programmable embedded MCU operation frequency. The operation can be 50MHz, 100MHz, and 125MHz.
  • Pipelined RISC architecture enables to execute instruction 10 times faster compared to standard 8051.
    • 24-bit FLAT program address mode.
    • 16-bit LARGE program address mode.
  • 24 times faster multiplication
  • 12 times faster addition.
  • Support 2 SPI ports and can be configured to be master/slave by programmers.
  • In SPI port 0, there are 8 bytes embedded buffer and the buffer length can be configured by MCU.
  • Support 1 master I2C port and there are 8 bytes embedded buffer which can be configured by MCU.
  • Support 2 UART ports.
  • Up to 256 bytes of internal on-chip data memory.
  • Total 128 bytes special function register (SFR).
  • Up to 8M bytes of external program memory.
  • Default 64KB of external programmable ROM size.
  • Embedded Fast Ethernet PHY and MAC which is fully compliant with IEEE 802.3/802.3u.
  • Support 10Mbps/100Mbps capability.
  • Support Full-duplex and half-duplex.
  • Embedded 32K bytes SRAM in receiving side.
  • Embedded 8K bytes SRAM in transmitting side.
  • Support auto-negotiation function to negotiate the correct speed and duplex mode.
  • In 100Mbps mode, the cable length can reach more than 110 meters.
  • In 10Mbps mode, the cable length can reach more than 150 meters.
  • Support auto-polarity detection function.
  • MAC function supports storing tag/untag information in SFR register.
  • MAC function supports storing source/destination IP address information in SFR register.
  • MAC function supports storing priority function information in SFR register.
  • MAC function supports storing port number information in SFR register.
  • Reserved IPv6 address in SFR register..
  • Embedded 10-bit ADC and controlled by MCU
    • There are 8 input channels to share the 10-bit ADC.
    • The fastest input sampling rate is up to1MHz.
    • Programmable ADC sampling frequency. There are four different sampling frequency and they are 1MHz, 500KHz, 250KHz, and 125KHz.
    • Two different sampling data output format.
    • ENoB can reach more than 8-bit.
  • Embedded four axles motor controller and controlled by MCU
    • The embedded four axles motor controller are independent for each other.
    • Support S-curve output pulse.
    • Support acceleration-curve output pulse.
    • Programmable duty cycle by SFR setting.
  • Embedded one channel frequency synthesizer and controlled by MCU.
    • Support two tones combiners..
    • Can generate sine and cosine functions waveforms or values.
    • Can generate ramp waveform or values.
    • Can generate triangle waveform or values.
  • Embedded one fast 8-bit X 8-bit multiplier and controlled by MCU
    • Only needs one cycle to compute the output value.

The input data can be 2's complement values.We can provide (1) RTL code; (2) Simulation environment; (3) FPGA down load file; (4) Synthesize constraint file; (5) Timing analysis constraint file; (6) Netlist file; (7) Netlist simulation environment

5. 8-port Ethernet switch IP

  • Fully compliant with IEEE 802.3/802.3u.
  • Support GMII/MII/RMII mode
  • Support 1k MAC address
  • Support broadcast storm protection
  • Support port security option to lock the first MAC address
  • Support one MII/RMII port, which works at 100M full duplex for router application
  • Support port base VLAN & tag VLAN
  • Support SMART MAC function
  • Support spanning tree protocol
  • Support max forwarding packet length 1552/1536 bytes option
  • Support two fiber ports with far end fault function.

We can provide (1) RTL code; (2) Simulation environment; (3) FPGA down load file; (4) Synthesize constraint file; (5) Timing analysis constraint file; (6) Netlist file; (7) Netlist simulation environment

6. FFT & IFFT engine

  • SMIC 0.18um CMOS logic process
  • High operation speed (200MHz)
  • Low power FFT & IFFT engine
  • Support variable length FFT & IFFT function
  • Support power saving mode for FFT & IFFT respectively.

Length: 64/128/256/512/1024/2048/4096 points
We can provide (1) RTL code; (2) Simulation environment; (3) FPGA down load file; (4) Synthesize constraint file; (5) Timing analysis constraint file; (6) Netlist file; (7) Netlist simulation environment

7. 3.3V to 1.8V regulator

  • SMIC 0.18um CMOS logic process
  • Support over 200mA current

We can provide (1) Analog design netlist; (2) Simulation environment; (3) GDS hard macro file

8. 10-bit SAR ADC for

  • 10-bit ADC
  • SNR is 55dB at full range of 0~3.3V in 3.3V supply.
  • Power supply range is from 3.3V.
  • Vref must less than Vsupply
  • 1LSB = Vref/1024
  • System clock is (125K*16)Hz
  • Operation current (including Bias and Vref): 1.2mA

We can provide (1) Analog design netlist; (2) Simulation environment; (3) GDS hard macro file

9. 6-bit 125M Analog to Digital Converter

  • SMIC 0.18um CMOS logic process.
  • 3.0~3.6Vdd power input.

We can provide (1) Analog design netlist; (2) Simulation environment; (3) GDS hard macro file

 

 

 

 

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